56F807 Datasheet, PDF (1/52 Pages) Motorola, Inc – 56F807 16-bit Hybrid Processor

Freescale Semiconductor, Inc.
DSP56F807/D
Rev. 12.0, 02/2004
56F807
Technical Data
56F807 16-bit Hybrid Processor
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Up to 64K × 16- bit words each of external
Program and Data memory
• Two 6 channel PWM Modules
• Hardware DO and REP loops
• Four 4 channel, 12-bit ADCs
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 60K × 16-bit words Program Flash
• 2K × 16-bit words Program RAM
• 8K × 16-bit words Data Flash
• 4K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCE^TM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 160-pin LQFP or 160 MAPBGA Packages
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
6
PWM Outputs
3
Current Sense Inputs
Fault Inputs
4
4
A/D1 _ADCA
4
A/D2 _VREF
4
A/D1 _ADCB
A/D2
4
VREF2
Quadrature
Decoder 0
4
/Quad Timer
PWMA
PWMB
RSTO
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VPP VCAPC V_DD V_SS V_DDA
2
8
10* 3
V_SSA
3
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quadrature
Decoder 1
Program Memory
4
/Quad Timer B
61440 x 16 Flash
2048 x 16 SRAM
Quad Timer C
2
Boot Flash
Quad Timer D
2048 x 16 Flash
4
/ Alt Func
CAN 2.0A/B
Data Memory
2
SCI0
8192 x 16 Flash
4096 x 16 SRAM
or
2
GPIO
SCI1
or
2
GPIO
COP/
Watchdog
SPI
Applica-
or
tion-Specific
4
GPIO
Memory &
Dedicated
GPIO
Peripherals
14
••
PAB
PDB
•
XDB2
•
CGDB
• _XAB1
• _XAB2
• _INTERRUPT
IPBB
•
CONTROLS CONTROLS
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
CLKO
XTAL
EXTAL
External ₆
Address Bus
A[00:05]
A[06:15] or
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
GPIO-E2:E3 &
10 _GPIO-A0:A7
D[00:15]
16
PS Select
Bus
DS Select
Control
WR Enable
RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F807 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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