56F801 Datasheet, PDF (24/44 Pages) Motorola, Inc – 56F801 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
11
10
9
8
7
6
5
0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
Figure 14. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25^oC
3.5.5 Phase Locked Loop Timing
Table 23. PLL Timing
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL¹
f_osc
4
8
10
MHz
PLL output frequency²
f_out/2
40
—
80³
MHz
PLL stabilization time⁴ 0^o to +85^oC
t_plls
—
10
—
ms
PLL stabilization time⁴ -40^o to 0^oC
t_plls
—
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f_out/2, please refer to the OCCS chapter
in the User Manual. ZCLK = f_op
3. Will not exceed 60MHz for the DSP56F801FA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
24
56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com