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56F801 Datasheet, PDF (1/44 Pages) Motorola, Inc – 56F801 16-bit Hybrid Controller | |||
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Freescale Semiconductor, Inc.
DSP56F801/D
Rev. 13.0, 02/2004
56F801
Technical Data
56F801 16-bit Hybrid Controller
⢠Up to 30 MIPS operation at 60MHz core
frequency
⢠Up to 40 MIPS operation at 80MHz core
frequency
⢠DSP and MCU functionality in a unified,
C-efficient architecture
⢠MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
⢠Hardware DO and REP loops
⢠6-channel PWM Module
⢠Two 4-channel, 12-bit ADCs
⢠Serial Communications Interface (SCI)
⢠8K à 16-bit words Program Flash
⢠1K à 16-bit words Program RAM
⢠2K à 16-bit words Data Flash
⢠1K à 16-bit words Data RAM
⢠2K à 16-bit words Boot Flash
⢠Serial Peripheral Interface (SPI)
⢠General Purpose Quad Timer
⢠JTAG/OnCETM port for debugging
⢠On-chip relaxation oscillator
⢠11 shared GPIO
⢠48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4
A/D2 ADC
4
VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD
2
4
VSS
5*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 â 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2
GPIO
COP/
Watchdog
Application-
SPI
Specific
4
or
GPIO
Memory &
Peripherals
â¢â¢
PAB
PDB
â¢
XDB2
â¢
CGDB
â¢
XAB1
⢠XAB2
⢠INTERRUPT
IPBB
â¢
CONTROLS CONTROLS
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
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