PC33889 Datasheet, PDF (19/30 Pages) Motorola, Inc – System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface

PC33889
Freescale Semiconductor, Inc.
Transitions to enter debug modes
W/D: time out 350ms
Normal Request
Reset counter
(1ms) expired
Reset
Power
Down
Normal
SPI: MCR (0000) & Normal Debug
Normal Debug
SPI: MCR (0000) & Standby Debug
Standby Debug
Stop (1)
Wake up
Simplified State machine in debug modes
W/D: time out 350ms
Normal Request
Reset counter
(1ms) expired
Reset
Wake up
R
R
R
W/D: _Trigger
R
R
R
Stop debug
Standby
SPI: _{normal debug}
E
Normal
E
Sleep
Standby Debug
SPI: Standby debug
SPI: Normal debug
Normal Debug
R
R
(1) If stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) debug mode entry point (step 5 of the debug mode entering sequence).
(R) represents transitions to reset mode due to Vdd1 low.
PC33889
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