PC33889 Datasheet, PDF (15/30 Pages) Motorola, Inc – System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface

PC33889
Freescale Semiconductor, Inc.
Figure 5. Reset and Wdogb function diagram
Watchdog time out
Vdd1
Reset
WDOGB
SPI
W/D clear
SPI CSB
Watchdog
period
Watchdog register addressed
The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to sig-
nal MCU wrong operation. Even if it is internally turned on (low sate) the reset pins can be forced to 5V at 25°C only, thanks to
its internal limited current drive capability. Wdogb stays low until the Watchdog register is properly addressed through SPI.
4.16 Debug mode Application hardware and software debug with the SBC.
When the SBC is mounted on the same printed circuit board as the micro controller it supplies, both application software and
SBC dedicated routine must be debugged. Following features allow the user to debug the software by allowing the possibility to
disable the SBC internal software watchdog timer.
4.16.1 Device power up, reset pin connected to Vdd1
At SBC power up, the Vdd1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
every 350ms. In order to allow software debug and avoid MCU reset the Reset pin can be connected directly to Vdd1 by a jumper.
4.16.2 Debug modes with software watchdog disabled though SPI (Normal Debug, Standby Debug and Stop Debug)
The software watchdog can be disabled through SPI. In order to avoid unwanted watchdog disable and to limit the risk of
disabling the watchdog during SBC normal operation the watchdog disable has to be done with the following sequence:
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode)
Step 3) Write to TIM1 register to allow SBC to enter Normal mode
Step 4) Write to MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
Step 5) Write to MCR register normal debug (0001 x101), standby debug (0001 x110) or Stop debug (0001 x111)
While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and
hardware debug.
Step 6) To leave the debug mode, write 0000 to MCR register.
To avoid entering debug mode after a power up, first read BATFAIL bit (MCR read) and write 0000 into MCR.
The graph below illustrates the debug mode entering.
Figure 6. Debug mode enter
VSup
Vdd1
Batfail
TIM1(step 3)
MCR (step5)
SPI
MCR(step4)
SPI: read batfail
MCR (step6)
debug mode
SBC in debug Mode, no W/D ^{SBC not in debug Mode and W/D on}
4.16.3 MCU flash programming configuration
In order to allow the possibility to download software into the application memory (MCU EEPROM or Flash) the SBC allows
the following capabilities: The Vdd1 can be forced by an external power supply to 5V and the reset and Wdogb outputs by
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