MC145572EVK Datasheet, PDF (18/52 Pages) Motorola, Inc – ISDN U-Interface Transceiver Evaluation Kit

Freescale Semiconductor, Inc.
The timing diagrams for each of these modes are shown in Figure 2-5 and Figure 2-6. One example of a
bit error rate test set-up is explained in the following section.
DCL
FSR
DOUT
DIN
(TSEN)
"
LTSFAR
NTSFAR
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D
LTGTCLK
NTGTCLK
NOTE: These clocks are available only when either OR7(b5) or OR8(b3) is set to 1. The example shown is for when the MC145572
is conÞgured as follows: BR7(b0)=1, OR7(b5)=1, OR8(b3)=1.
Figure 2-5. BERT Gated Clock Ñ 8-Bit Gated Clock
DCL
FSR
DOUT
DIN
B1 B1 B1 B1 B1 B1 B1 B1 D
B2 B2 B2 B2 B2 B2 B2 B2 D
B1 B1 B1 B1 B1 B1 B1 B1 D
B2 B2 B2 B2 B2 B2 B2 B2 D
(TSEN)
LTSF"AR
NTSFAR
LTGTCLK
NTGTCLK
NOTE: These clocks are available only when either OR7(b5) or OR8(b3) is set to 1. The example shown is for when the MC145572
is conÞgured as follows: BR7(b0)=0, OR7(b5)=1, OR8(b3)=1.
Figure 2-6. BERT Gated Clock Ñ 10-Bit Gated Clock
MOTOROLA
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MC145572EVK
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