DSP56852 Datasheet, PDF (17/44 Pages) Motorola, Inc – DSP56852 16-bit Digital Signal Processor

Freescale Semiconductor, Inc.
Supply Voltage Sequencing and Separation Cautions
V_DD should not be allowed to rise early (1). This is usually avoided by running the regulator for the V_DD
supply (1.8V) from the voltage generated by the 3.3V V_DDIO supply, see Figure 5. This keeps V_DD from
rising faster than V_DDIO.
V_DD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically
this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 5.
The series diodes forward bias when the difference between V_DDIO and V_DD reaches approximately 2.1,
causing V_DD to rise as V_DDIO ramps up. When the V_DD regulator begins proper operation, the difference
between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
V_DDIO > V_DD > (V_DDIO - 2.1V)
In practice, V_DDA is typically connected directly to V_DDIO with some filtering.
3.3V
Supply ^Regulator
V_DDIO, V_DDA
1.8V
V_DD
Regulator
Figure 5. Example Circuit to Control Supply Sequencing
DSP56852 Technical Data
17
Preliminary
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