DSP56852 Datasheet, PDF (1/44 Pages) Motorola, Inc – DSP56852 16-bit Digital Signal Processor

Freescale Semiconductor, Inc.
DSP56852/D
Rev. 6.0 2/2004
DSP56852
Preliminary Technical Data
DSP56852 16-bit Digital Signal Processor
• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines
and four chip selects
• One (1) Serial Port Interface (SPI) or one (1)
Improved Synchronous Serial Interface (ISSI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog
Timer
• 81-pin MAPBGA package
• Up to 11 GPIO
• One (1) Serial Communication Interface (SCI)
Memory
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
6
JTAG/
Enhanced
OnCE
V_DDIO
6
V_DD VSSIO VSS VDDA VSSA
3
63
16-Bit
DSP56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System
Bus
Control
A0-16
A17-18 muxed (timer pins)
A19 muxed (CS3)
D0-D12[12:0]
D13-15 muxed (Mode A,B,C)
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
System
Address
Decoder
System
Device
IPBus Bridge (IPBB)
Peripheral
Address
Decoder
Decoding
Peripherals
Peripheral
Device
Selects
RW
IPAB
Control
IPWDB
IPRDB
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
Bus Control
Clock
resets
SCI or
GPIOE
2
1 Quad
Timer
or A17,
A18
2
SSI or
SPI or
GPIOC
6
COP/
Watch-
dog
Interrupt
Controller
P
O
R
System
Integration
Module
PLL
Clock
O
S
Generator _C
IRQA
IRQB
3
CLKO
RESET
MODE
muxed (A20)
muxed (D13-15)
Figure 1. DSP56852 Block Diagram
XTAL
EXTAL
© Motorola, Inc., 2004. All rights reserved.
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