MC145170-2 Datasheet, PDF (15/32 Pages) Motorola, Inc – PLL Frequency Synthesizer with Serial Interface

Freescale Semiconductor, Inc.
Pin Connections
ENB
CLK
1
2
3
4
5
6
7
8
*
MSB
LSB
D_in
C7 C6
C5
C4 C3
C2 C1
C0
* At this point, the new byte is transferred to the C register and stored. No other registers are affected.
C7 - POL:
Select the output polarity of the phase/frequency detectors. When set high, this
bit inverts PD_out and interchanges the φ_R function with φ_V as depicted in
Figure 19. Also see the phase detector output pin descriptions for more
information. This bit is cleared low at power up.
C6 - PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the
output of phase/frequency detector A (PD_out) and disables phase/frequency
detector B by forcing φ_R and φ_V to the static high state. When cleared low,
phase/frequency detector B is enabled (φ_R and φ_V) and phase/frequency detector
A is disabled with PD_out forced to the high-impedance state. This bit is cleared
low at power up.
C5 - LDE: Enables the lock detector output when set high. When the bit is cleared low, the
LD output is forced to a static low level. This bit is cleared low at power up.
C4 - C2, OSC2 - OSC0:
Reference output controls which determines the REF_out characteristics as shown
below. Upon power up, the bits are initialized such that OSC_in/8 is selected.
C4
C3
C2
REF_out Frequency
0
0
0 dc (Static Low)
0
0
1
OSC_in
0
1
0
OSC_in/2
0
1
1
OSC_in/4
1
0
0
OSC_in/8 (POR
Default)
1
0
1
OSC_in/16
1
1
0
OSC_in/8
1
1
1
OSC_in/16
C1 - f_VE:
C0 - f_RE:
Enables the f_V output when set high. When cleared low, the f_V output is forced to
a static low level. The bit is cleared low upon power up.
Enables the f_R output when set high. When cleared low, the f_R output is forced to
a static low level. The bit is cleared low upon power up.
Figure 16. C Register Access and Format (8 Clock Cycles are Used)
MOTOROLA
MC145170-2 Technical Data
15
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