DSP56F802 Datasheet, PDF (13/32 Pages) Motorola, Inc – DSP56F802 16-bit Digital Signal Processor

DC Electrical Characteristics
Table 15. DC Electrical Characteristics
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50 pF, f_op = 80 MHz
Characteristic
Symbol
Min
Typ Max Unit
PWM pin output source current¹
I_OHP
—
—
-10
mA
PWM pin output sink current²
I_OLP
—
—
16
mA
V_DD supply current
I_DDT3
Run⁴
—
103 138
mA
Wait⁵
—
72
98
mA
Stop
—
60
84
mA
Low Voltage Interrupt⁶
Core Voltage Interrupt
V_EI
2.4
2.7 2.9
V
—
2.2
—
Power on Reset⁷
POR
—
1.7 2.0
V
1. PWM pin output source current measured with 50% duty cycle.
2. PWM pin output sink current measured with 50% duty cycle.
3. I_DDT = I_DD + I_DDA (Total supply current for VDD + VDDA)
4. Run (operating) I_DD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
5. Wait I_DD measured using internal relaxation oscillator set to 8 MHz; all inputs 0.2V from rail; no DC loads; less
than 50 pF on all outputs. C_L = 20 pF on EXTAL; all ports configured as inputs; measured with PLL enabled.
6. Low voltage interrupt monitors the V_DD supply. When V_DD drops below V_EI value, an interrupt is generated.
Functionality of the device is guaranteed under transient conditions when V_DDA>V_EI.
7. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below V_POR. While power is
ramping up, this signal remains active for as long as the internal 2.5V supply is below 1.5V no matter how long the ramp
up rate is. The internally regulated voltage is typically 100 mV less than V_DD during ramp up until 2.5V is reached, at
which time it self regulates.
180
150
120
90
60
30
0
0
Digital (VDD=3.6V)
20
Analog (VDDA=3.6V)
40
60
Freq. (MHz)
Total
80
Figure 3. Maximum Run Idd vs. Frequency (see Note 4 above)
MOTOROLA
DSP56F802 Preliminary Technical Data
13