DSP56F802 Datasheet, PDF (1/32 Pages) Motorola, Inc – DSP56F802 16-bit Digital Signal Processor

DSP56F802/D
Rev. 0, 1/2002
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
• Up to 40 MIPS operation at 80 MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Hardware DO and REP loops
• 6-channel PWM Module with fault input
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• Serial Communications Interface (SCI)
• Two General Purpose Quad Timers with 2
external outputs
• JTAG/OnCE^TM port for debugging
• 4 shared GPIO
• On-chip relaxation oscillator
• 32-pin LQFP Package
PWM Outputs
6
Fault A0
2 ^A/D1
3
A/D2 ADC
VREF
PWMA
RESET
5
JTAG/
OnCE
Port
VCAPC V_DD
2
2
V_SS* V_DDA
3
V_SSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Quad Timer D
2
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2
GPIO
COP/
Watchdog
Application-
Specific
Memory &
Peripherals
••
PAB
PDB
•
PLL
XDB2
Relaxation
.
Oscillator
•
CGDB
XAB1
XAB2
•
•
•
•
INTERRUPT
IPBB
CONTROLS CONTROLS
16-Bit
DSP56800
Core
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F802 Block Diagram
© Motorola, Inc., 2002. All rights reserved.