MC68331 Datasheet, PDF (12/84 Pages) Motorola, Inc – User’s Manual

Freescale Semiconductor, Inc.
Table 6 MCU Signal Function (Continued)
Signal Name
Boot Chip Select
Data Bus
Data Strobe
Data and Size Acknowledge
Development Serial In, Out,
Clock
Crystal Oscillator
Function Codes
Freeze
Halt
Input Capture
Input Capture 4/Output Compare
5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
Clock Mode Select
Master Out Slave In
Output Compare
Pulse Accumulator Input
Port C
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
Port F
Port QS
Pulse-Width Modulation
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
Three-State Control
SCI Transmit Data
External Filter Capacitor
Mnemonic
CSBOOT
DATA[15:0]
DS
DSACK[1:0]
DSI, DSO,
DSCLK
EXTAL, XTAL
FC[2:0]
FREEZE
HALT
IC[3:1]
IC4/OC5
Function
Chip select for external boot startup ROM
16-bit data bus
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
Can be configured for either an input capture or output compare
IPIPE, IFETCH Indicate instruction pipeline activity
IRQ[7:1] Provides an interrupt priority level to the CPU
MISO
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
MODCLK Selects the source and type of system clock
MOSI
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
OC[5:1]
Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
PAI
Signal input to the pulse accumulator
PC[6:0] SIM digital output port signals
PCLK
External clock dedicated to the GPT
PCS[3:0] QSPI peripheral chip selects
PE[7:0] SIM digital I/O port signals
PF[7:0] SIM digital I/O port signals
PQS[7:0] QSM digital I/O port signals
PWMA, PWMB Output for PWM
QUOT
Provides the quotient bit of the polynomial divider
RESET System reset
RMC
Indicates an indivisible read-modify-write instruction
R/W
Indicates the direction of data transfer on the bus
RXD
Serial input to the SCI
SCK
Clock output from QSPI in master mode;
clock input to QSPI in slave mode
SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle
SS
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
TSC
Places all output drivers in a high-impedance state
TXD
Serial output from the SCI
XFC
Connection for external phase-locked loop filter capacitor
12
For More Information On This Product,
MC68331TS/D
Go to: www.freescale.com