DSP56307 Datasheet, PDF (12/156 Pages) Motorola, Inc – 24-BIT DIGITAL SIGNAL PROCESSOR

Signals/Connections
External Memory Expansion Port (Port A)
Signal
Name
PINIT
NMI
Table 1-5 Phase-Locked Loop Signals (Continued)
Type
Input
State During
Reset
Signal Description
Input
PLL InitialÑDuring assertion of RESET, the value of
PINIT is written into the PLL enable (PEN) bit of the
PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Input
Nonmaskable InterruptÑAfter RESET deassertion
and during normal instruction processing, this
Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
EXTERNAL MEMORY EXPANSION PORT (PORT A)
Note:
When the DSP56307 enters a low-power standby mode (stop or wait), it
releases bus mastership and tri-states the relevant Port A signals: A0ÐA17,
D0ÐD23, AA0/RAS0ÐAA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
External Address Bus
Signal
Name
A0ÐA17
Table 1-6 External Address Bus Signals
Type
Output
State During
Reset
Signal Description
Tri-stated
Address BusÑWhen the DSP is the bus master,
A0ÐA17 are active-high outputs that specify the
address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To
minimize power dissipation, A0ÐA17 do not
change state when external memory spaces are not
being accessed.
Not Recommended for New Design
1-6
DSP56307 Technical Data
MOTOROLA