DSP56307 Datasheet, PDF (1/156 Pages) Motorola, Inc – 24-BIT DIGITAL SIGNAL PROCESSOR

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24-BIT DIGITAL SIGNAL PROCESSOR
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DSP56307DS/D
Rev. 0, 8/10/98
DSP56307
The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal
processors (DSPs), supports wireless infrastructure applications with general filtering
operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in
parallel with core operation, thus increasing overall DSP performance and efficiency. Like the
other family members, the DSP56307 uses a high-performance, single-clock-cycle-per-instruction
engine (code-compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit
addressing, an instruction cache, and a direct memory access controller, as in Figure 1. The
DSP56307 offers performance at 100 million instructions (MIPS) per second using an internal
100 MHz clock with a 2.5 volt core and independent 3.3 volt input/output power.
3
16
66
Memory Expansion Area
SCI
Interface
Triple
Timer
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
Host
Interface
HI08
ESSI
Interface
Enhanced
Filtering
Co-
processor
EFCOP
Peripheral
Expansion Area
Program
RAM
16 K × 24 or
(Program
RAM
15 K × 24 and
Instruction
Cache
1024 × 24)
X Data
RAM
24 K × 24
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Y Data
RAM
24 K × 24
External
Address
Bus
Switch
18
Address
External
Bus
Interface
and
I - Cache
Control
13
Control
External
Data Bus
Switch
24
Data
Clock
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
PLL
Interrupt
Controller
2
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24+56^→56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1 DSP56307 Block Diagram
Power
Mngmnt.
5
JTAG
OnCE™
DE
AA1367
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without
notification.
Not Recommended for New Design
©1998 MOTOROLA, INC.