MCM69C232 Datasheet, PDF (11/20 Pages) Motorola, Inc – 4K x 64 CAM

12,000
10,000
8,000
TYPICAL
6,000
4,000
WORST CASE
2,000
0
180
280
380
480
580
680
780
880
980
MATCH CYCLE TIME AT 50 MHz INPUT CLOCK
Figure 3. Connections per Second vs Match Cycle Time
TIMING OVERVIEW
CONTROL PORT
The control port of the MCM69C232 is asynchronous.
Data transfers, both read and write, are initiated by the
assertion of the SEL signal. Address values should be valid,
and WE should be high, when SEL is asserted to begin
a read cycle. All values (address, WE, and SEL) should be
held until the MCM69C232 asserts DTACK to signal the end
of the read cycle.
Address and data values should be valid, and WE should
be low, when SEL is asserted to begin a write cycle. Address,
data, WE, and SEL values should be held until the
MCM69C232 asserts DTACK to signal the end of the write
cycle.
MATCH PORT
v ^{The MCM69C232’s match port is synchronous in opera-}
tion. When the match width is 32 bits, a match cycle can
be initiated by presenting the match data on MQ31 – MQ0
and asserting the LH/SM signal with the appropriate setup
time relative to the rising edge of the clock. The assertion of
the MC output signifies the completion of the match cycle. If
a match has been found, the MS output is also asserted. If
the match is a virtual path circuit match in ATM mode, the
VPC output will be asserted with the MS output. Output data,
if any, is enabled by the assertion of the G input.
If the match width is greater than 32 bits, the lower bits are
first latched into the MCM69C232 by the LL input. The match
cycle is then initiated as specified in the previous paragraph.
DEPTH EXPANSION
Multiple CAMs can be cascaded to increase the depth of
the match table. The hardware requirements are very
straightforward, as the following pins on each device are sim-
ply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ,
DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.
Four CAMs can be easily cascaded. Simulations show that
eight devices can be cascaded if care is taken to minimize
the length of the PC board traces connecting the CAMs.
The buffered entry mode prevents multiple matching en-
tries in a single CAM. The check for value instruction should
be used to verify that multiple matching entries will not result
from a potential new entry. If a match is found in CAM 1, for
example, the new value should be placed in CAM 1, where it
will replace the existing entry.
MOTOROLA FAST SRAM
MCM69C232
11