MCM69C232 Datasheet, PDF (1/20 Pages) Motorola, Inc – 4K x 64 CAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM69C232/D
Advance Information
4K x 64 CAM
The MCM69C232 is a flexible content–addressable memory (CAM) that can
contain 4096 entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 160 ns. As a result,
the MCM69C232 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C232 is
user defined, with a trade–off between the time between matches and the num-
ber of new entries added to the CAM per second.
• 4096 Entries
• 160 ns Match Time
• Mask Register to “Don’t Care” Selected Bits
• Depth Expansion by Cascading Multiple Devices
• 50 MHz Maximum Clock Rate
• Programmable Match and Output Field Widths
• Concurrent Matching of Virtual Path Circuits and Virtual Connection
Circuits in ATM Mode
• Separate Ports for Control and Match Operations
• 200 ns Insertion Time if One of Twelve Entry Queue Locations is Empty
• 12 ms Initialization Time After Fast Insertion (at Power–Up Only)
• Single 3.3 V ± 5% Supply
• 100 Pin TQFP Package
• IEEE Standard 1149.1 Test Port (JTAG)
Related Products
— MCM69D536, MCM69D618 (Dual I/O, Dual Address RAMs)
— MCM67Q709A, MCM67Q909 (Separate I/O RAMs)
— MCM69C432 (CAM)
CONTROL PORT
12 x 64
ENTRY QUEUE
A2 – A0
DQ15 – DQ0
SEL
WE
IRQ
DTACK
RESET
STATUS/
CONTROL
LOGIC
INPUT REG
4K x 64
CAM
TABLE
MCM69C232
TQ PACKAGE
TQFP
CASE 983A–01
MATCH PORT
MQ31 – MQ0
K
G
LH/SM
LL
MC
MS
VPC
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
1/15/98
©_MM_Oo_Tto_Orol_Ra,_OInc_L._A19_F98_{AST SRAM}
MCM69C232
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