MC33592FTA Datasheet, PDF (11/28 Pages) Motorola, Inc – PLL Tuned UHF Receiver for Data Transfer Applications

Freescale Semiconductor, Inc.
CONFIGURATION REGISTERS
- DME enables the Data Manager:
0 = Disabled,
1 = Enabled.
Data are output on MOSI and the associated clock on SCLK.
- HE defines if a Header word is present (the bit HE is only active if DME=1):
0 = No header,
1 = Header.
Configuration Register 2 (CR2) defines the Identifier (ID) word content. The bits will be Manchester coded.
Bit name
Reset value
Table 7: Configuration Register 2
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0
0
0
0
0
0
0
0
Table 8 describes the Configuration Register 3 (CR3).
Bit name
Reset value
Table 8: Configuration Register 3
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DR1 DR0 MG MS PG
-
-
-
1
0
0
0
0
0
0
0
- DR0/DR1 define the Data Rate (before Manchester coding) as shown onTable 9.
Table 9: Data Rate selection
DR1 DR0
Selected Ratio
0
0
0
1
1
0
1.0 - 1.4 kBd
2 - 2.7 kBd
4 - 5.3 kBd
1
1
8.6 - 10.6 kBd
- MG sets the mixer gain:
0 = Normal,
1 = -17dB (typical).
- MS switches the MIXOUT pin:
0 = To the mixer output,
1 = To the IF input.
Table 10: Mixer and MIXOUTconfiguration
MG MS
Mixer Gain
MIXOUT
0
0
Normal
Mixer output
0
1
Normal
IF input
1
0
Reduced
Mixer output
1
1
Forbidden, mixer test mode only
The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a test mode where
the mixer runs at f_VCO/4.
- PG sets the phase comparator gain (see “The local oscillator PLL” chapter, page 4):
0 = High gain mode,
1 = Low gain mode.
MOTOROLA
MC33592 Technical Data
11
For More Information On This Product,
Go to: www.freescale.com