DSP56F826 Datasheet, PDF (10/44 Pages) Motorola, Inc – Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor

Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
1. When a pn is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Signal
Name
Pin No.
Type
Description
IRQA
32 Input
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge- triggered. If
level-sensitive triggering is selected, an external pull up resistor is required
for wired-OR operation.
IRQB
MISO
33 Input
86 Input/Output
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-
sensitive triggering is selected, an external pull up resistor is required for
wired-OR operation.
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if the slave device is not
selected.
GPIOF6
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
MOSI
85 Input/Output
After reset, the default state is MISO.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device
uses to latch the data.
GPIOF5
PS
RD
Input/Output
29 Output
26 Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
Program Memory Select—PS is asserted low for external program memory
access.
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the DSP data bus. When RD is deasserted high, the external
data is latched inside the DSP. When RD is asserted, it qualifies the A0–A15,
PS, and DS pins. RD can be connected directly to the OE pin of a Static
RAM or ROM.
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DSP56F826 Preliminary Technical Data