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DSP56F826 Datasheet, PDF (1/44 Pages) Motorola, Inc – Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor | |||
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Semiconductor Products Sector
DSP56F826/D
Rev. # 0, 3/2001
DSP56F826
Preliminary Technical Data
DSP56F826 16-bit Digital Signal Processor
⢠Up to 40 MIPS at 80MHz core frequency
⢠DSP and MCU functionality in a unified,
C-efficient architecture
⢠Hardware DO and REP loops
⢠MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
⢠31.5K à 16-bit words Program Flash
⢠512 à 16-bit words Program RAM
⢠2K à 16-bit words Data Flash
⢠4K à 16-bit words Data RAM
⢠2K à 16-bit words BootFLASH
⢠Up to 64K à 16-bit words each of external
memory expansion for Program and Data
memory
⢠One Serial Port Interface (SPI)
⢠One additional SPI or two optional Serial
Communication Interfaces (SCI)
⢠One Synchronous Serial Interface (SSI)
⢠One General Purpose Quad Timer
⢠JTAG/OnCE⢠for debugging
⢠100-pin LQFP Package
⢠16 dedicated and 30 shared GPIO
⢠One Time-of-Day module
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VDD
3
IO
VSS VDD
34
IO
VSS
4
VDDA VSSA
Low Voltage Supervisor
Analog Reg
TOD
Timer
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 â 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Program Memory
Quad Timer
32252 x 16 Flash
or
512 x 16 SRAM
4
GPIO
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
SSI
4096 x 16 SRAM
or
6
GPIO
SCI0 & SCI1
or
4
SPI0
SPI1
or
4
GPIO
Dedicated
GPIO
16
COP/
Watchdog
Application-
Specific
Memory &
Peripherals
PAB
PDB
COP
RESET
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
16
IPBB
CONTROLS
16
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
DSP56800
Core
PLL
Clock Gen
.
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
CLKO
XTAL
EXTAL
A[00:15]
or
16 GPIO
D[00:15]
16
PS Select
DS Select
WR Enable
RD Enable
Figure 1. DSP56F826 Block Diagram
© Motorola, Inc., 2001. All rights reserved.
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