MTD6N10E Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 6.0 AMPERES 100 VOLTS RDS(on) = 0.400 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD6N10E/D
™ Designer's Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
• Replaces MTD5N10
®
D
S
MTD6N10E
Motorola Preferred Device
TMOS POWER FET
6.0 AMPERES
100 VOLTS
RDS(on) = 0.400 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
100
Vdc
VDGR
100
Vdc
VGS
± 20
Vdc
VGSM
± 40
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
6.0
Adc
ID
4.5
IDM
18
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG =25 Ω)
PD
TJ, Tstg
EAS
40
0.32
1.75
– 55 to 150
50
Watts
W/°C
Watts
°C
mJ
Thermal Resistance — Junction to Case
R_θJC
3.13
°C/W
Thermal Resistance — Junction to Ambient
R_θJA
100
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
R_θJA
71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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