MTD20N06HDL Datasheet, PDF (1/12 Pages) Motorola, Inc – TMOS POWER FET LOGIC LEVEL 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
bt MTD20N06HDL/D
Advance Information
HDTMOS E-FETā™
High Density Power FET
DPAK for Surface Mount or
Insertion Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits, and inductive loads. The avalanche energy
capability is specified to eliminate the guesswork in designs where
inductive loads are switched, and to offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Specified
G
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
• Available in Insertion Mount, Add –1 or 1 to Part Number
™
D
S
MTD20N06HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
60 VOLTS
RDS(on) = 0.045 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain–Source Voltage
VDSS
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
Drain Current — Continuous @ 25°C
ID
Drain Current — Continuous @ 100°C
ID
Drain Current — Single Pulse (tp ≤ 10 µs)
IDM
Total Power Dissipation
PD
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
Operating and Storage Temperature Range
TJ, Tstg
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R_θJC
R_θJA
R_θJA
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
(1) When surface mounted to an FR–4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Value
60
60
± 15
± 20
20
12
60
40
0.32
1.75
– 55 to 150
200
3.13
100
71.4
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
REV 1
©^MM^oot^to^oro^rola^l,^aIn^Tc.^M19^O9^S6 ^{Power MOSFET Transistor Device Data}
1