MTB75N03HDL Datasheet, PDF (1/12 Pages) Motorola, Inc – TMOS POWER FET LOGIC LEVEL 75 AMPERES 25 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advanced Information
HDTMOS E-FET.™
High Density Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
™
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
D
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
G
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
S
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Ultra Low RDS(on), High–Cell Density, HDTMOS
• Short Heatsink Tab Manufactured — Not sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MTB75N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
75 AMPERES
25 VOLTS
RDS(on) = 9 mOHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
VDGR
VGS
VGSM
25
25
± 15
± 20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
ID
75
ID
59
IDM
225
PD
125
1.0
2.5
Operating and Storage Temperature Range
– 55 to 150
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R_θJC
R_θJA
R_θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
(1) When mounted with the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
280
1.0
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
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