MTB50N06VL Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 42 AMPERES 60 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB50N06VL/D
™ Designer's Data Sheet
TMOS V™
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
MTB50N06VL
Motorola Preferred Device
TMOS POWER FET
42 AMPERES
60 VOLTS
RDS(on) = 0.032 OHM
TM
D
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
G
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETs
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
CASE 418B–02, Style 2
S
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
60
Vdc
VDGR
60
Vdc
VGS
± 15
Vdc
VGSM
± 20
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 42 Apk, L = 0.3 mH, RG = 25 Ω)
ID
ID
IDM
PD
TJ, Tstg
EAS
42
30
147
125
0.83
3.0
– 55 to 175
265
Adc
Apk
Watts
W/°C
Watts
°C
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R_θJC
R_θJA
R_θJA
1.2
°C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©^MM^oo^tt^oo^rr^ool^la^a, I^Tnc^M. 1^O99^S6 ^{Power MOSFET Transistor Device Data}
1