MC54-74HC366 Datasheet, PDF (1/5 Pages) Motorola, Inc – Hex 3-State Inverting Buffer with Common Enables

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex 3-State Inverting Buffer
with Common Enables
High–Performance Silicon–Gate CMOS
The MC54/74HC366 is identical in pinout to the LS366. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is a high–speed hex buffer with 3–state outputs and two
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC366 has
inverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 78 FETs or 19.5 Equivalent Gates
LOGIC DIAGRAM
A0 ²
A1 ⁴
A2 ⁶
A3 ¹⁰
A4 ¹²
OUTPUT ENABLE 1 ¹
OUTPUT ENABLE 2 ¹⁵
A5 ¹⁴
3 _Y0
5 _Y1
7 _Y2
9 _Y3
11 _Y4
13 _Y5
PIN 16 = VCC
PIN 8 = GND
MC54/74HC366
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
Ceramic
Plastic
PIN ASSIGNMENT
OUTPUT
ENABLE 1
1
A0 2
Y0 3
16 VCC
15
OUTPUT
ENABLE 2
14 A5
A1 4
13 Y5
Y1 5
12 A4
A2 6
11 Y4
Y2 7
10 A3
GND 8
9 Y3
FUNCTION TABLE
Inputs
Enable Enable
1
2
A
Output
Y
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
X = don’t care
Z = high impedance
10/95
© Motorola, Inc. 1995
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