V58C265404S Datasheet, PDF (9/44 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4

MOSEL VITELIC
V58C265404S
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
(CAS Latency = 2.5; Burst Length = 4)
T0
T1
T2
T3
T4
CK, CK
Command
READ
NOP
DQS
DQ
NOP
t_DQSCK
NOP
NOP
t_DQSCK(max)
t_DQSCK(min)
t_AC
D₀
t_AC(min)
t_AC(max)
D₁
D₂
D₃
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-
ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (t_DV) and minimum data strobe valid time (t_DQSV) are de-
rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
V58C265404S Rev. 1.4 January 2000
9