V58C265404S Datasheet, PDF(18/44 Page) Mosel Vitelic, Corp – HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4

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V58C265404S Datasheet, PDF (18/44 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4

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MOSEL VITELIC

V58C265404S

Write Interrupted by a Precharge

A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only

restriction being that the interval that separates the commands be at least one clock cycle. When the previous

burst is interrupted, the remaining addresses are overridden by the new address and data will be written into

the device until the programmed burst length is satisfied.

Write Interrupted by a Precharge Timing

(CAS Latency = 2; Burst Length = 8)

T10 T11 T12

CK, CK

Command

DQS

WriteA NOP

NOP

PreA NOP

tWR

NOP

D0 D1 D2 D3 D4 D5

Data is masked

by DM input

Data is masked

by Precharge Command

DQS input ignored

Write with Auto Precharge

If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any

new command to the same bank should not be issued until the internal precharge is completed. The internal

precharge begins after keeping tWR (min.).

Write with Auto Precharge Timing

(CAS Latency = Any; Burst Length = 4)

CK, CK

Command

BA NOP

DQS

tRAS(min)

NOP

WAP

NOP

tWR(min)

D0 D1 D2 D3

tRP(min)

NOP

Begin Autoprecharge

V58C265404S Rev. 1.4 January 2000

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