V62C1804096 Datasheet, PDF (8/10 Pages) Mosel Vitelic, Corp – 512K X 8, CMOS STATIC RAM

MOSEL VITELIC
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)⁽⁴⁾
ADDRESS
CE1
CE2
WE
OUTPUT
INPUT
t_AS
t_WHZ
t_WC
t_CW(6)
t_AW
t_CW(6)
t_WP(1)
t_DW
V62C1804096
t_WR(2)
t_DH
Write Cycle 2 (CE Controlled)⁽⁴⁾
ADDRESS
CE1
CE2
WE
t_WC
(4)
t_AW
t_AS
t_CW(6)
t_CW(6)
t_WR(2)
OUTPUT
INPUT
High-Z
t_DW
t_DH
(5)
NOTES:
1. The internal write time of the memory is defined by the overlap of CE₁ and CE₂ active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2. t_WR is measured from the earlier of CE₁ or WE going high, or CE₂ going LOW at the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = V_IL or V_IH. However it is recommended to keep OE at V_IH during write cycle to avoid bus contention.
5. If CE₁ is LOW and CE₂ is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6. t_CW is measured from CE₁ going low or CE₂ going HIGH to the end of write.
V62C1804096 Rev. 1.0 October 2001
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