V62C1804096 Datasheet, PDF (5/10 Pages) Mosel Vitelic, Corp – 512K X 8, CMOS STATIC RAM

MOSEL VITELIC
V62C1804096
Data Retention Characteristics
Symbol
V_DR
I_CCDR
Parameter
V_CC for Data Retention
CE₁ ≥ V_CC – 0.2V, CE₂ < 0.2V, V_IN ≥ V_CC – 0.2V,
or V_IN ≤ 0.2V
Data Retention Current
CE₁ ≥ V_DR – 0.2V, CE₂ < 0.2V, V_IN ≥ V_CC – 0.2V,
or V_IN ≤ 0.2V, V_DR = 1.0V
Com’l
Ind.
t_CDR
Chip Deselect to Data Retention Time
t_R
Operation Recovery Time (see Retention Waveform)
NOTES:
1. t_RC = Read Cycle Time
2. T_A = +25°C.
Power
L
LL
L
LL
Min.
1.0
—
—
—
—
0
t_RC(1)
Typ.⁽²⁾
—
1
0.5
—
—
—
—
Max.
2.3
3
1.5
5
2
—
—
Units
V
µA
ns
ns
Low V_CC Data Retention Waveform (1) (CE₁ Controlled)
Data Retention Mode
V_CC
1.8V
V_DR ≥ 1V
1.8V
t_CDR
t_R
CE₁
1.6V
CE₁ ≥ V_CC – 0.2V
1.6V
V62C1804096 Rev. 1.0 October 2001
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CHANGING:
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
5