V54C365404VD Datasheet, PDF (8/54 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4

MOSEL VITELIC
V54C365404VD(L)
Burst Length and Sequence:
Burst Starting Address Sequential Burst Addressing
Length
(A2 A1 A0)
(decimal)
2
xx0
0, 1
xx1
1, 0
4
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
8
000
001
010
011
100
101
110
111
01234567
12345670
23456701
34567012
45670123
56701234
67012345
70123456
Full
nnn
Page
Cn, Cn+1, Cn+2,.....
Interleave Burst Addressing
(decimal)
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
01234567
10325476
23016745
32107654
45670123
54761032
67452301
76543210
not supported
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge com-
mand is necessary. A minimum tRC time is required
between two automatic refreshes in a burst refresh
mode. The same rule applies to any access com-
mand after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one t_RC delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and write
operations. During reads, when it turns to “high” at a
clock timing, data outputs are disabled and become
high impedance after two clock delay (DQM Data
Disable Latency t_DQZ ). It also provides a data mask
function for writes. When DQM is activated, the write
operation at the next clock is prohibited (DQM Write
Mask Latency t_DQW = zero clocks).
Suspend Mode
During normal access mode, CKE is held high en-
abling the clock. When CKE is low, it freezes the in-
ternal clock and extends data read and write
operations. One clock delay is required for mode en-
try and exit (Clock Suspend Latency t_CSL).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay (trp)
must occur before the SDRAM can enter the Power
Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver
circuits except CLK and CKE are gated off. The
Power Down mode does not perform any refresh
operations, therefore the device can’t remain in
Power Down mode longer than the Refresh period
(tref) of the device. Exit from this mode is performed
by taking CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
V54C365404VD(L) Rev. 0.9 September 2001
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