V54C365404VD Datasheet, PDF (14/54 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4

MOSEL VITELIC
V54C365404VD(L)
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have V_IL = 0.8V and V_IH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between V_IH and V_IL. All AC measurements assume t_T = 1ns with the AC output load circuit shown
in Figure 1.
CLK
COMMAND
tCK
tCS tCH
1.4V
tAC
tLZ
VIH
VIL
t_T
tAC
tOH
+ 1.4 V
50 Ohm
Z=50 Ohm
I/O
50 pF
OUTPUT
1.4V
tHZ
Figure 1.
4. If clock rising time is longer than 1 ns, a time (t_T/2 – 0.5) ns has to be added to this parameter.
5. If t_T is longer than 1 ns, a time (t_T – 1) ns has to be added to this parameter.
6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
V54C365404VD(L) Rev. 0.9 September 2001
14