V62C1802048L Datasheet, PDF (5/9 Pages) Mosel Vitelic, Corp – Ultra Low Power 256K x 8 CMOS SRAM

V62C1802048L(L)
Timing Waveform of Read Cycle 1 ^(3,6,7,9) (Address Controlled)
Address
D_OUT
t_RC
t_AA
t_OH
Data Valid
Timing Waveform of Read Cycle 2 ^(5,6,8,9) (CE1 Controlled)
t_RC
CE1
OE
t_OE
D_OUT
t_OLZ
t_ACE
t_OHZ
t_CHZ
Data Valid
t_CLZ
t_PD
Supply Current
t_PU
I_CC
50%
50%
I_SB
Timing Waveform of Read Cycle 3 ^(3,6,8,9) (CE2 Controlled)
t_RC
CE2
OE
t_OE
D_OUT
t_OLZ
t_ACE
t_OHZ
t_CHZ
Data Valid
t_CLZ
t_PD
Supply Current
t_PU
I_CC
50%
50%
I_SB
5
REV. 1.2 May 2001 V62C1802048L(L)