V62C1802048L Datasheet, PDF (1/9 Pages) Mosel Vitelic, Corp – Ultra Low Power 256K x 8 CMOS SRAM

V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single + 1.8 to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
ive LOW OE , and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1) with Write Enable (WE) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
INPUT BUFFER
A0
A1
A2
I/O8
A3
A4
A5
Cell Array
A6
A7
A8
I/O1
A9
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
OE
CONTROL WE
CIRCUIT ^CE1
CE2
A11
1
A9
2
A8
3
A13
4
WE
5
CE2
6
A15
7
Vcc
8
A17
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
1
REV. 1.2 May 2001 V62C1802048L(L)
32
OE
31
A10
30
CE1
29
I/O8
28
I/O7
27
I/O6
26
I/O5
25
I/O4
24
GND
23
I/O3
22
I/O2
21
I/O1
20
A0
19
A1
18
A2
17
A3