V58C365164S Datasheet, PDF (16/44 Pages) Mosel Vitelic, Corp – 64 Mbit DDR SDRAM 4M X 16, 3.3VOLT

MOSEL VITELIC
V58C365164S
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to
Output Disable latency is equivalent to the CAS latency.
Read Interrupted by a Precharge Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t_RAS(min)
t_RP(min)
CK, CK
Command ^{BA NOP}
NOP
Read
NOP
Pre_A
NOP
BA
NOP
NOP
DQS
DQ
D₀ D₁ D₂ D₃
CAS Latency=2
DQS
DQ
D₀ D₁ D₂ D₃
CAS Latency=2.5
DQS
DQ
D₀ D₁ D₂ D₃
CAS Latency=3
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. The memory controller is re-
quired to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and
data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required
to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be
driven high nominally one clock after the write command has been registered. Timing parameters t_DQSS(min)
and t_DQSS(max) define the allowable window when the data strobe must be driven high.
Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is regis-
tered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the
data strobe signal. The data window is defined by DQ to DQS setup time (t_QDQSS) and DQ to DQS hold time
(t_QDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst
length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
Write Preamble and Postamble Operation
Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”.
This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write com-
mand has been registered by the device. The preamble is explicitly defined by a setup time (t_WPRES(min)) and
hold time (t_WPREH(min)) referenced to the first falling edge of CK after the write command.
V58C365164S Rev. 1.7 March 2002
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