V58C265804S Datasheet, PDF (12/44 Pages) Mosel Vitelic, Corp – HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

MOSEL VITELIC
V58C265804S
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A₁₀ high when a Read or Write
command is issued. If A₁₀ is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once t_RAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. If a Read with autoprecharge command is issued before t_RAS(min) is satisfied, the
precharge operation will be delayed until that time when t_RAS(min) is met. Once the autoprecharge opera-
tion has begun, the bank cannot be reactivated until the minimum precharge time (t_RP) has been satisfied.
Read with Autoprecharge Timing
T0
CK, CK
Command
DQS
DQ
(CAS Latency = 2; Burst Length = 4)
T1
T2
T3
T4
T5
T6
T7
T8
T9
t_RAS(min)
t_RP(min)
BA
NOP R w/AP NOP
NOP
NOP
NOP
BA
NOP
D₀ D₁ D₂ D₃
Begin Autoprecharge
Earliest Bank A reactivate
V58C265804S Rev. 1.3 January 2000
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