AA057VG02 Datasheet, PDF (9/22 Pages) Mitsubishi Electric Semiconductor – TECHNICAL SPECIFICATION

6. INTERFACE TIMING
(1) Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX. UNIT
Frequency
DCLK

Period
Low Width
High Width
DATA(R,G,B), ^{Set up time}
DENA _{Hold time}
Active Time

Blanking Time
Horizontal
Frequency
DENA
Period
Active Time

Blanking Time
Vertical
Frequency
Period
fCLK
tCLK
tWCL
tWCH
tDS
tDH
tHA
tHB
fH
tH
tVA
tVB
fV
tV
20
33.3
10
10
4
4
640
20
27
26.3
480
4
55
14.3
25
40
--
--
--
--
640
160
31.5
31.7
480
45
60
16.7
30
50
--
--
--
--
640
--
38
37.0
480
--
70
18.2
MHz
ns
ns
ns
ns
ns
tCLK
tCLK
kHz
μs
tH
tH
Hz
ms
[Note]
1) DATA is latched at fall edge of DCLK in this specification.
2) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
3) DCLK should appear during all invalid period.
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
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AA057VG02_02_00