MH32S64APHB-6 Datasheet, PDF (8/55 Pages) Mitsubishi Electric Semiconductor – 2,147,483,648-BIT (33,554,432 - WORD BY 64-BIT)Synchronous DRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S64APHB -6,-7,-8
2,147,483,648-BIT (33,554,432 - WORD BY 64-BIT)Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS /CAS /WE BA0,1 A11
A10 A0-9
DESEL
NOP
H XHX X X X
H XL H H H X
XXX
XXX
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V V
Single Bank Precharge PRE
H XL L H L V X L X
Precharge All Bank
PREA
H XL L H L X X H X
Column Address Entry
& Write
WRIT E
H XL H L
L
VVL
V
Column Address Entry
& Write with Auto-
WRITEA H X L H L
L
V
VHV
Precharge
Column Address Entry
& Read
READ
H XL H L H V V L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
READA
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H XL H L H V V H V
H HL L L H X X X X
H LL L L H X X X X
L HH X X X X X X X
L HL H H H X X X X
H XL H H L X X X X
H X L L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0379-0.1
MITSUBISHI
ELECTRIC
( 8 / 55 )
17.Mar.2000