MH32S64APHB-6 Datasheet, PDF (25/55 Pages) Mitsubishi Electric Semiconductor – 2,147,483,648-BIT (33,554,432 - WORD BY 64-BIT)Synchronous DRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S64APHB -6,-7,-8
2,147,483,648-BIT (33,554,432 - WORD BY 64-BIT)Synchronous DRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank .
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-
precharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
A0-9,11
A10
Write
Ya
1
Write
BL
Ya
0
tWR
ACT
tRP
Xa
Xa
BA0,1
00
10
00
DQ
Da0 Da1 Db0 Db1 Db2 Db3
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2,BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
Write
Ya
Read
BL
Yb
1
0
00
10
Da0 Da1
tWR
ACT
tRP
Xa
Xa
00
Db0 Db1 Db2 Db3
auto-precharge interrupted
activate
MIT-DS-0379-0.1
MITSUBISHI
ELECTRIC
( 25 / 55 )
17.Mar.2000