M2V28S20TP Datasheet, PDF (7/52 Pages) Mitsubishi Electric Semiconductor – 128M Synchronous DRAM

SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND
MNEMONIC ^{CKE CKE} /CS /RAS /CAS /WE BA0,1 A11 A10 A0-9
n-1 n
Deselect
DESEL
HX HXXX X X XX
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
NOP
ACT
PRE
H X L HHH X X X X
H X L L HH V V V V
HX L LHL VX LX
Precharge All Banks
Column Address Entry
& Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
PREA
WRITE
WRITEA
READ
READA
REFA
HX L L HL X XHX
HXLHLL VVLV
HX LHL L V VHV
HX L HLH V V L V
HX LHLH V VHV
HHLL LHXXXX
Self-Refresh Entry
REFS
HL LL LHXXXX
Self-Refresh Exit
REFSX
L HHXXX X X XX
L H L HHH X X X X
Mode Register Set
MRS
HX
L
L
L
L
L
L
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
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