M2V28S20TP Datasheet, PDF (31/52 Pages) Mitsubishi Electric Semiconductor – 128M Synchronous DRAM

SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
AC TIMING REQUIREMENTS
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Input Pulse Levels:
0.8V – 2.0V
Input Timing Measurement Level:
1.4V
Symbol
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
Parameter
CLK cycle time
CL=2
CL=3
CLK High pulse width
CLK Low pulse width
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Delay time
Mode Register Set Cycle time
Self-refresh Exit time
Power Down Exit time
Refresh Interval time
-6
Min.
Max.
10
7.5
2.5
2.5
1
10
1.5
0.8
67.5
20
45
100K
20
15
15
15
7.5
7.5
64
Limits
-7
Min.
Max.
10
10
3
3
1
10
2
1
70
20
50
100K
20
20
20
20
10
10
64
-8
Unit
Min.
Max.
13
ns
10
ns
3
ns
3
ns
1
10 _ns
2
ns
1
ns
70
ns
20
ns
50
100K _ns
20
ns
20
ns
20
ns
20
ns
10
ns
10
ns
64 _ms
CLK
DQ
1.4V
1.4V
Any AC timing is referenced
to the input signal passing
through 1.4V.
MITSUBISHI ELECTRIC
31