M37640E8 Datasheet, PDF (69/172 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER

Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
INTST3, INTST5, INTST7 or INTST9 is set to a “1” by the USB FCU if (in Endpoint xOUT CSR):
• Successfully receives a packet of data
• OUTXCSR1 (OVER_RUN) bit is set
• OUTXCSR4 (FORCE_STALL) bit is set
MSB
7
INTST15 INTST14 INTST13 INTST12 Reserved Reserved INTST9
INTST8
INTST9
USB Endpoint 4 In Interrupt Status Flag (bit 0)
USB Endpoint 4 Out Interrupt Status Flag (bit 1)
INTST8
LSB
0
Bit 3:2
Reserved (Read/Write “0”)
INTST12
INTST13
INTST14
INTST15
USB Overrun/Underrun Interrupt Status Flag (bit 4)
USB Reset Interrupt Status Flag (bit 5)
USB Resume Signaling Interrupt Status Flag (bit 6)
USB Suspend Signaling Interrupt Status Flag (bit 7)
0: No interrupt request issued
1: Interrupt request issued
Figure 2-68. USB Interrupt Status Register 2
Address: 0053₁₆
Access: R/W
Reset: 00₁₆
INTST12 is set to a “1” by the USB FCU if an overrun or underrun condition occurs in any of the
endpoints.
INTST13 is set to a “1” by the USB FCU if a USB reset signaling from the host is received. All
USB internal registers will be reset to their default values except this bit.
INTST14 is set to a “1” by the USB FCU if a USB resume signaling is received from the host.
INTST15 is set to a “1” by the USB FCU if a USB suspend signaling is received from the host.
MSB
7
INTEN7 INTEN6
INTEN0
INTEN5 INTEN4 INTEN3 INTEN2 Reserved
USB Endpoint 0 In Interrupt Enable Bit (bit 0)
INTEN0
LSB
0
Bit 1
Reserved (Read/Write “0”)
INTEN2
INTEN3
INTEN4
INTEN5
INTEN6
INTEN7
USB Endpoint 1 IN Interrupt Enable Bit (bit 2)
USB Endpoint 1 OUT Interrupt Enable Bit (bit 3)
USB Endpoint 2 IN Interrupt Enable Bit (bit 4)
USB Endpoint 2 OUT Interrupt Enable Bit (bit 5)
USB Endpoint 3 IN Interrupt Enable Bit (bit 6)
USB Endpoint 3 OUT Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
Figure 2-69. USB Interrupt Enable Register 1
Address: 0054₁₆
Access: R/W
Reset: FF₁₆
MSB
7
INTEN15 Reserved
INTEN8
INTEN9
INTEN13 INTEN12 Reserved Reserved INTEN9
USB Endpoint 4 IN Interrupt Enable Bit (bit 0)
USB Endpoint 4 OUT Interrupt Enable Bit (bit 1)
INTEN8
LSB
0
Bit 3:2
Reserved (Read/Write “0”)
INTEN12
INTEN13
USB Overrun/Underrun Interrupt Enable Bit (bit 4)
USB Reset Interrupt Enable Bit (bit 5)
Bit 6
Reserved (Read/Write “0”)
INTEN15
USB Suspend/Resume Signaling Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
Figure 2-70. USB Interrupt Enable Register 2
Address: 0055₁₆
Access: R/W
Reset: 33₁₆
Universal Serial Bus
7/9/98
2-57