PS51259-A Datasheet, PDF (6/6 Pages) Mitsubishi Electric Semiconductor – TRANSFER-MOLD TYPE INSULATED TYPE

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51259-A
TRANSFER-MOLD TYPE
INSULATED TYPE
DIP-PFC Wiring Guidelines
Because DIP-PFC switches large current at a very high speed, considerable large surge voltage is generated easily between P and N termi-
nals. Please pay attention to the following items:
• The area of P-Co-N shown in Fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. In
addition, please add a bypass condenser Co’ with good frequency response such as a polypropylene film condenser closely to the P and N
terminals.
• The two IGBT emitters are connected to the VNO terminal of LVIC inside the DIP-PFC. If the internal wiring inductance shown as L1 and L2
in Fig. 4 is too large, large surge voltage will be generated by di/dt. Especially, the lower the temperature, the faster the switching speed,
therefore the larger the di/dt. This surge voltage applies to the VNO and N terminals, which is possible to destruct LVIC.
• In order to suppress the surge voltage, the external wiring method shown in Fig. 4 is recommended. To reduce the parasitic wiring induc-
tance, the wiring of the external terminals of N(N-1) and N(N-2) should be made as short as possible.
• Please mount a fast clamp diode (EG01Y@Sanken) between N and control GND terminals to prevent control GND potential variation from
the minus voltage of N terminal.
Fig. 3 DIP-PFC INTERFACE
DIP • PFC
P
N/F
VD
GND
R
S
LVIC
VNO
VIN
+
Co'
Co
N2
N
(N-1, N-2)
MCU
Control IC
Fig. 4 RECOMMENDED WIRING METHOD
+
To restrain the IPM surge voltage,
mount the condenser closely to the
terminals
To reduce the parasitic inductance,
this wire should close to N terminal
Insert a diode here
P
S
R
L2 _N-1
L1
N-2
N2
N2
GND
VD
VIN
GND
VD
+
Control input
Mar. 2003