MH4V36AM-6 Datasheet, PDF (6/18 Pages) Mitsubishi Electric Semiconductor – FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Read write/read modify write cycle time (Note22)
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
(Note23)
Delay time, RAS low to W low
(Note23)
Delay time, address to W low
(Note23)
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time _{ÅbeÜfore} W low
ÅÜ
Data hold time afÅteÖr W low
ÅÖ
OE hold time after W low
Limits
-6
-7
Min
Max
Min
Max
155
180
105
10000
120
10000
60
10000
70
10000
105
120
60
70
0
0
40
45
85
95
55
60
15
20
15
20
10
10
0
0
10
15
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+5tT.
23: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Symbol
Parameter
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
RAS low pulse width for read write cycle (Note25)
CAS high pulse width
RAS hold time after CAS precharge
(Note26)
Delay time, CAS precharge to W low (Note23)
Limits
-6
-7
Min
Max
Min
Max
40
45
85
95
100
125000
115
125000
10
15
10
15
35
40
60
65
Unit
ns
ns
ns
ns
ns
ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
25: tRAS(min) is specified as two cycles of CAS input are performed.
26: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle (Note 27)
Symbol
Parameter
tCSR CAS setup time before RAS low
tCHR CAS hold time after RAS low
tRSR
Read setup time before RAS low
tRHR
Read hold time after RAS low
Limits
-6
Min
Max
-7
Unit
Min
Max
10
10
ns
10
15
ns
10
10
ns
10
15
ns
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh
mode.
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 6 / 18 )
Sep./19 /1996