M5M4V4265CJ Datasheet, PDF (6/31 Pages) Mitsubishi Electric Semiconductor – EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
90
110
130
ns
50 10000 60 10000 70 10000
ns
8 10000 10 10000 10 10000
ns
40
48
55
ns
13
15
20
ns
(Note 24) 0
0
0
ns
8
10
13
ns
8
10
13
ns
8
10
13
ns
8
10
13
ns
0
0
0
ns
8
10
13
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
tRWC
Read write/read modify write cycle time
(Note 23) 109
133
161
ns
tRAS
RAS low pulse width
tCAS
CAS low pulse width
tCSH
CAS hold time after RAS low
tRSH
RAS hold time after CAS low
tRCS
Read setup time before CAS low
75 10000 89 10000 107 10000
ns
38 10000 44 10000 57 10000
ns
70
82
99
ns
38
44
57
ns
0
0
0
ns
tCWD
Delay time, CAS low to W low
(Note 24) 28
32
42
ns
tRWD
Delay time, RAS low to W low
(Note 24) 65
77
92
ns
tAWD
Delay time, address to W low
(Note 24) 40
47
57
ns
tOEH
OE hold time after W low
13
15
20
ns
Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M4V4265CJ,TP-5,-5S:under development