M37754M8C-XXXGP Datasheet, PDF (54/114 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
Transmission is started when bit 0 (TEi flag) of UARTi Transmit/Re-
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ceive control register 1 is “1”, bit 1 (TIi flag) is “0”, and CTSi input is
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“L” if CTSi input is selected. As shown in Figures 65 and 66, data is
output from the TXDi pin with the stop bit or parity bit specified by bits
4 to 6 of UARTi Transmit/Receive mode register. The data is output
from the least significant bit.
The TIi flag indicates whether the transmit buffer is empty or not. It is
cleared to “0” when data is written in the transmit buffer, and is set to
“1” when the contents of the transmit buffer register is transferred to
the transmit register.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied.
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Once transmission has started, the TEi flag, TIi flag, and CTSi signal
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(if CTSi input is selected ) are ignored until data transmission is com-
pleted.
Therefore, transmission does not stop until it completes event if the
TEi flag is cleared during transmission.
The transmission start condition indicated by TEi flag, TIi flag, and
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CTSi is checked while the TENDi signal shown in Figure 65 is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
Bit 3 (TXEPTYi flag) of UARTi Transmit/Receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interrupt control register is set to “1”.
Transmission clock
(1/Pfi or 1/fEXT) × (n + 1) × 16
TEi
TIi
CTSi
Written in transmit buffer register
Transmit register ← Transmit
buffer register
TENDi
TXDi
Start bit
Parity bit Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped because TEi = “0”
ST D0 D1
TXEPTYi
Fig. 65 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
Transmission clock
TEi
TIi
TENDi
TXDi
TXEPTYi
(1/Pfi or 1/fEXT) × (n + 1) × 16
Written in transmit buffer register
Transmit register ← Transmit
buffer register
Start bit
Stop bit Stop bit
Stopped because TEi = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2
Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
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