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M5M417400CJ Datasheet, PDF (5/22 Pages) Mitsubishi Electric Semiconductor – FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted. See notes 12, 13)
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
Max
Min
Max
Min
Max
tREF
Refresh cycle time
32
32
32
ms
tRP
RAS high pulse width
30
40
50
ns
tRCD
Delay time, RAS low to CAS low
(Note 14)
18
37
20
45
20
50
ns
tCRP
Delay time, CAS high to RAS low
10
10
10
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tCPN
CAS high pulse width
10
10
10
ns
tRAD
Column address delay time from RAS low
(Note 15)
13
25
15
30
15
35
ns
tASR
Row address setup time before RAS low
0
0
0
ns
tASC
Column address setup time before CAS low
(Note 16)
0
10
0
10
0
10
ns
tRAH
Row address hold time after RAS low
8
10
10
ns
tCAH
Column address hold time after CAS low
13
15
15
ns
tDZC
Delay time, data to CAS low
(Note 17)
0
0
0
ns
tDZO
Delay time, data to OE low
(Note 17)
0
0
0
ns
tCDD
Delay time, CAS high to data
(Note 18)
13
15
15
ns
tODD
Delay time, OE high to data
(Note 18)
13
15
15
ns
tT
Transition time
(Note 19)
1
50
1
50
1
50
ns
Note 12:
13:
14:
15:
16:
17:
18:
19:
The timing requirements are assumed tT = 5ns.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by
tCAC or tAA. tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tH + tASC(min).
tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
Either tDZC or tDZO must be satisfied.
Either tCDD or tODD must be satisfied.
tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tOCH
tORH
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time after CAS high
Read hold time after CAS low
Read hold time after RAS low
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
Limits
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
Max
Min
Max
Min
Max
90
110
130
ns
50
10000
60
10000
70
10000
ns
13
10000
15
10000
20
10000
ns
50
60
70
ns
13
15
20
ns
0
0
0
ns
(Note 20)
0
0
0
ns
(Note 20)
10
10
10
ns
25
30
35
ns
13
15
20
ns
13
15
20
ns
Note 20: Either tRCH or tRRH must be satisfied for a read cycle.
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