MH8S72BMG-7 Datasheet, PDF (47/55 Pages) Mitsubishi Electric Semiconductor – 603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Self-Refresh
CLK
/CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK can be stopped
tRC
/RAS
/CAS
/WE
CKE
DQM
tSRX
CKE must be low to maintain Self-Refresh
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI
ELECTRIC
( 47 / 55 )
29. Oct.1998