MH8S72BMG-7 Datasheet, PDF (1/55 Pages) Mitsubishi Electric Semiconductor – 603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH8S72BMG is 8388608 - word by 72-bit
Synchronous DRAM module. This consists of ten
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-7
100MHz
6.0ns(CL=3)
-8
100MHz
6.0ns(CL=3)
-10 100MHz
8.0ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0222-0.5
MITSUBISHI
ELECTRIC
( 1 / 55 )
29. Oct.1998