MH32S72APHB-6 Datasheet, PDF (44/55 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S72APHB -6,-7,-8
2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM
Read Interrupted by Read / Write @BL=4 CL=3
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
/CAS
tRRD
tRCD
/WE
CKE
DQM
DQM read latency=2
A0-8
X
XY
YY
Y
Y
Y
A10
X
X
A9,11
X
X
BA0,1
0
10
00
1
0
0
DQ
Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0
D0 D0
ACT#0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0380-0.1
MITSUBISHI
ELECTRIC
( 44 / 55 )
17.Mar.2000