MH32S72APHB-6 Datasheet, PDF (1/55 Pages) Mitsubishi Electric Semiconductor – 2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S72APHB -6,-7,-8
2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM
DESCRIPTION
The MH32S72APHB is 33554432 - word by 72-bit
Synchronous DRAM module. This consists of
eighteen industry standard 16Mx8 Synchronous
DRAMs in TSOP and one industory standard
EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-6
133MHz
5.4 ns(CL=3)
-7
100MHz
6.0ns(CL=2)
-8
100MHz
6.0ns(CL=3)
Utilizes industry standard 16M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin ^84pin
APPLICATION
PC main memory
MIT-DS-0380-0.1
MITSUBISHI
ELECTRIC
( 1 / 55 )
17.Mar.2000