MH8S72DBFD-7 Datasheet, PDF (39/56 Pages) Mitsubishi Electric Semiconductor – 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Buffer mode(REGE="L")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
tRRD
tRCD
/WE
CKE
DQM
A0-9
X
XY
Y
X
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
DQ
REGE
10
1 01
D0 D0 D0 D0 D1 D1
1
1
D1 D1 D1
ACT#0 WRITE#0
ACT#1
PRE#0
WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted
by Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
MIT-DS-0351-0.0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
30/Sep. /1999 ₃₉